Forming lines or gaps with extremely small structure widths represents one of the major challenges in the fabrication of integrated circuits. This applies in particular to the fabrication of memory cell arrays with volatile or non-volatile memory concepts. If the minimum structure widths of insulated or semi-insulated line structures that can be achieved in the course of processing are compared with those of insulated or semi-insulated trench structures, then it is possible to ascertain considerably better results on the part of line patterning. This holds true for the line structures that are exposed in a resist and developed after the step of development as resist ridges, and also for the structures that are transferred from the resist ridges into an underlying layer in an etching process.
Hereinafter, the terms lines and ridges, and respectively gaps and trenches, are in each case intended to be used synonymously.
This is caused by fundamental optical effects, which adversely affect the result to a lesser extent precisely in the case of insulated or semi-insulated lines. However, there are some memory cell concepts that rely on the patterning of gap or trench structures. One example thereof may be found in the so-called NROM (non-volatile read-only memory) cell concepts.
It is endeavored, therefore, to implement the fabrication of trench structures with exposure steps that are carried out in projection apparatuses of particularly high resolution, in order to compensate for this disadvantage. However, the requisite outlay is very high, in particular the costs of such projection apparatuses also playing an important part. Moreover, the process window that can also be achieved with these apparatuses is very small on account of the property of the trenches that the latter are present in insulated or semi-insulated fashion, and this may give rise to bridges in the resist and/or poor contrast in the image produced in the resist. Therefore, a lithography with projection apparatuses having the 157 nm or 193 nm wavelength does not constitute a suitable solution approach.
One alternative is to use projection apparatuses having lower resolution, i.e., having exposure wavelengths in the deep ultraviolet wavelength range (DUV), for example 248 nm, in combination with so-called shrink technologies. These include the use of silylation techniques (CARL), resist reflow techniques or techniques in which gaps or contact holes are reduced in size by the reaction of a chemical with the patterned resist. However, such techniques are not yet entirely mature at the present time, with the result that intolerable CD variations (CD: critical dimension) may occur precisely in the limit range of extremely minimal structure widths.
Instead of combining deep ultraviolet exposure with shrink technology, the latter may also be combined with the use of a negative resist. Insulated and opaque lines arranged on a mask provided for the projection lead to shaded line regions in the resist on the wafer. However, it is not the exposed regions around the line, but rather the unexposed regions of the line itself, which are stripped out in the subsequent development process. The advantage that occurs due to the reduction of the fundamental optical effects mentioned above is cancelled, however, by the disadvantage of the unfavorable resolution properties that are inherent to all known and commercially available negative resists.
In accordance with an integrative solution, a so-called spacer process is introduced in addition to a low-resolution lithography step (e.g., DUV lithography) during the post processing. Comparatively, wide trenches formed in the lithography step are overgrown by a small thickness from the side by the deposition of a thin layer, for example made of oxide. The thin layer is subsequently etched back anisotropically in large-area fashion. The layer that has grown laterally at the trench walls and remains after the etching-back step is referred to as spacer. The width remaining in the trench can be set by control of the deposition and etching process. In the case of this solution approach, too, the costs are very high because it is necessary to introduce an additional deposition and etching process in the fabrication sequence. The line width fluctuations also rise as a result of the multiplicity of processes. Consequently, tolerances that are usually prescribed can often no longer be complied with. Moreover, the additional deposition and etching processes lead to contamination problems.